1. Field of the Invention
The present invention relates to a semiconductor storage device, and more particularly to the layout of power supply lines in a semiconductor storage device.
2. Description of the Related Art
FIG. 46 is a plan view illustrating a dynamic random access memory (DRAM) which is a conventional semiconductor storage device disclosed in, for instance, Japanese Unexamined Patent Publication No. Hei. 4-212454. In the drawing, reference numeral 101 denotes a region in which sense amplifiers are arrayed in a row (sense-amplifier forming region), 102 denotes a region in which a group of storage elements are arrayed (memory cell array), 103 denotes a region in which the sense-amplifier forming region 101 on the one hand, and a word-line backing region 104 for connecting a relatively high-resistance wiring and a low-resistance metal wiring formed in a layer separate from that wiring on the other hand, intersect each other. In addition, FIG. 47 is an enlarged view of the region denoted by a character X in FIG. 46, and illustrates the detail of the wiring of the power supply lines. In FIG. 47, numeral 105 denotes a power supply line for supplying power supply potential, 106 denotes a grounding line for supplying ground potential; and 107 and 108 denote through holes for connecting the power supply line 105 and the grounding line 106 extending in the horizontal direction (in this drawing) to the power supply line 105 and the grounding line 106 extending in the vertical direction (in this drawing).
Thus, in accordance with the prior art, as shown in FIG. 47, the power supply lines 105 and the grounding lines 106, extending in the vertical and horizontal directions in the sense-amplifier forming regions 101, are respectively connected to each other via the through holes 107 and 108, and are thereby arranged in mesh form. As the power supply lines 105 and the grounding lines 106 are thus arranged in mesh form, the supply of power to drive circuits for driving the sense amplifiers is effected speedily so as to speed up the operations of reading and writing information with respect to the memory cells.
In addition, if an assembly of the memory cells is denoted by memory portions 109a to 109d, an actual DRAM chip can be shown in FIG. 48. In this arrangement, row decoders 110a and 110b and column decoders 111a and 111b necessary for the designation of memory cells are arranged. The two memory portions 109a and 109c are disposed on both sides of the column decoder 111a extending in the direction of the rows, the memory portions 109b and 109d are disposed on both sides of the column decoder 111b, the memory portions 109a and 109b are disposed on both sides of the row decoder 110a extending in the direction of the columns, and the memory portions 109c and 109d are disposed on both sides of the row decoder 110b. 
Next, an enlarged view of a portion of FIG. 48, i.e., 111a a region including a boundary between the column decoder 111a and the memory portion 109c, is shown in FIG. 49. As already described, the power supply lines 105 and the grounding lines 106 are arranged on the memory portions 109a to 109d in mesh form, and extension lines of these wirings (105, 106) are also arranged on an adjacent column decoder 111a. 
Since the wirings (105, 106) are thus arranged in the region where the column decoder 111a is formed, the region where the column decoder 111a is effectively formed becomes small, so that it has been difficult to secure a space necessary for forming the column decoder 111a having a complicated configuration. In addition, since the power supply lines 105 and the grounding lines 106 are generally formed in an identical plane in the same process, it has been difficult to form a single power supply line by combining the plurality of power supply lines 105 (or grounding lines 106) without short-circuiting the power supply lines 105 and the grounding lines 106 or increasing the number of processes involved.
In addition, in the sense-amplifier forming regions 101 in the memory portions 109a to 109d, the power supply lines 105 extending in the direction of the columns and the power supply lines 105 extending in the direction of the rows, as well as the grounding lines 106 extending in the direction of the rows and the grounding lines 106 extending in the direction of the columns, are respectively connected together via the through holes 107 and 108. However, since these through holes require relatively large areas for formation, if an attempt is made to form a through hole at the respective intersections of the power supply lines 105 and the grounding lines 106, restrictions occur in the interval between the power supply line and the grounding line.
Meanwhile, in a synchronous DRAM, which is a type of DRAM, a plurality of banks which are assemblies of memory cells capable of operating independently are provided in a single semiconductor chip, and the banks operate simultaneously. The inputting and outputting of data to and from the banks for the inputting and outputting of external data are effected at high speed. While the operation of accessing a designated address X1, Y1 of one of the banks is being carried out, the operation of accessing a designated address X2, Y2 of another bank is carried out, and the inputting and outputting of external data by the two banks are effected by being delayed by one cycle each, thereby making a high-speed operation possible. In this synchronous DRAM, since the plurality of banks operate simultaneously, in a case where two banks operate simultaneously, power consumption twice that necessary for the operation of one bank is required, so that the supply of sufficient power is necessary.
The conventional semiconductor storage devices are configured as described above, and since the wirings including the power supply lines and the grounding lines are disposed on the column decoder, there has been a drawback in that the area where the column decoder is effectively formed becomes small.
In addition, in the case where the through holes are formed at the respective intersections of the power supply lines (or grounding lines) extending in the direction of the columns of the memory cells and the power supply lines (or grounding lines) extending in the direction of the rows thereof, there has been a problem in that restrictions occur in the interval between the power supply line and the grounding line.
Further, the power supply wiring for strengthening the power supplying capability is not formed in regions (shunt regions) for connecting a relatively high-resistance wiring and a low-resistance wiring, such as a metal wiring, via through holes in the case of a semiconductor storage device using a word line shunt system, and in regions for connecting main word lines and sub-word lines (regions where sub-decoding circuits are formed) in the case of a semiconductor storage device using a word line division system.
Furthermore, if there is a region where power consumption is large partially in a memory cell array, it is necessary to strengthen the power supplying capability with respect to the particular region. With the conventional methods, however, it has been difficult to improve the power supplying capability of a particular region. Further, since the conventional synchronous DRAM is formed as described above, power consumption twice that necessary for the operation of one bank is required. Consequently, there has been a drawback in that operations of banks, which should be independent of each other, affect each other due to a decline in the power supply potential depending on the method of supplying power to the memory cell array, resulting in the loss of leeway in the operation of the memory cell array.
The present invention has been devised to overcome the above-described drawbacks, and it is an object of the present invention to provide a semiconductor storage device which is capable of securing a column-decoder forming region without an increase in the number of manufacturing steps and which has sufficient power supplying capability.
According to a first aspect of the invention, there is provided a semiconductor storage device comprising:
a memory cell array including a plurality of memory cell sub-arrays in each of which a plurality of memory cells are arranged along row and column directions;
power supply lines extending along the row direction and arranged between the memory cell sub-arrays in a region where the memory cell array is formed; and
power supply lines extending along the column direction in the region where the memory cell array is formed, and including first power supplying lines for supplying a first potential and second power supplying lines for supplying a second potential, the second power supplying lines being so arranged that plural, adjacent ones of the first power supplying lines are interposed between the second power supplying lines.
According to a second aspect of the invention, there is provided a semiconductor storage device comprising:
a memory cell array including a plurality of memory cell sub-arrays in each of which a plurality of memory cells are arranged along row and column directions;
power supply lines extending along the row direction and arranged between the memory cell sub-arrays in a region where the memory cell array is formed; and
power supply lines extending along the column direction in the region where the memory cell array is formed, and including first power supplying lines for supplying a first potential and second power supplying lines for supplying a second potential, the power supply lines being arranged such that plural, adjacent ones of the first power supplying lines and plural, adjacent ones of the second power supplying lines are arranged alternately.
According to a third aspect of the invention, there is provided a semiconductor storage device comprising:
a memory cell array including a plurality of memory cell sub-arrays in each of which a plurality of memory cells are arranged along row and column directions;
power supply lines extending in the row direction and arranged between the memory cell sub-arrays in a region where the memory cell array is formed; and
power supply lines extending along the column direction in the region where the memory cell array is formed, and including first power supplying lines for supplying a first potential and second power supplying lines for supplying a second potential, the first power supplying lines and the second power supplying lines being arranged alternately, and at least one of the first power supplying lines and the second power supplying lines being formed such that a plurality of lines branch off at an end of the memory cell array and are arranged on the memory cell array.
According to a fourth aspect of the invention, there is provided a semiconductor storage device comprising:
a memory cell array including a plurality of memory cell sub-arrays each having a plurality of memory cell blocks in each of which a plurality of memory cells are arranged along row and column directions;
power supply lines extending along the row direction and arranged between the memory cell sub-arrays in a region where the memory cell array is formed; and
power supply lines extending along the column direction in the region where the memory cell array is formed, and including first power supplying lines for supplying a first potential and second power supplying lines for supplying a second potential, the first power supplying lines and the second power supplying lines being arranged alternately, and either the first power supplying lines or the second power supplying lines including lines that extend along the column direction on one of the memory cell blocks.
According to a fifth aspect of the invention, there is provided a semiconductor storage device comprising:
a memory cell array including a plurality of memory cell sub-arrays each having a plurality of memory cell blocks in each of which a plurality of memory cells are arranged along row and column directions;
power supply lines extending along the row direction and arranged between the memory cell sub-arrays in a region where the memory cell array is formed; and
power supply lines extending along the column direction in the region where the memory cell array is formed, and including first power supplying lines for supplying a first potential and second power supplying lines for supplying a second potential, the first power supplying lines and the second power supplying lines being arranged alternately, and at least one of the first power supplying lines and the second power supplying lines being formed such that a plurality of lines branch off at an end of the memory cell array and extend along the column direction on at least one of the memory cell blocks so as to be adjacent to each other.
According to a sixth aspect of the invention, there is provided a semiconductor storage device comprising:
a memory cell array including a plurality of memory cell sub-arrays in each of which a plurality of memory cells are arranged along row and column directions;
power supply lines extending along the row direction and arranged between the memory cell sub-arrays in a region where the memory cell array is formed;
power supply lines extending along the column direction in the region where the memory cell array is formed; and
signal lines so arranged that plural, adjacent ones of the power supply lines along the column direction are interposed between the signal lines.
According to a seventh aspect of the invention, there is providedf a semiconductor storage device comprising:
a memory cell array in which a plurality of memory cells are arranged in row and column directions;
sense amplifiers for sensing a state of each of the memory cells;
a sense amplifier block including plural ones of the sense amplifiers on which writing is performed simultaneously; and
a driver transistor formed in the sense amplifier block and connected to either of power supply lines extending along the row direction,
wherein of plural ones of the sense amplifiers connected to the power line along the row direction via the driver transistor, only one sense amplifier is subjected to writing simultaneously with the other sense amplifiers.
According to an eighth aspect of the invention, there is provided a semiconductor storage device comprising:
a memory cell array including a plurality of memory cell sub-arrays in each of which a plurality of memory cells are arranged along row and column directions, the memory cell array including a plurality of memory cell sub-arrays that are activated simultaneously;
power supply lines extending along the row direction and arranged between the memory cell sub-arrays in a region where the memory cell array is formed;
power supply lines extending along the column direction in the region where the memory cell array is formed, and including first power supplying lines for supplying a first potential and second power supplying lines for supplying a second potential; and
a through hole for connecting a power supply line along the row direction and a power supply line along the column direction, the through hole being formed at a position which is closest to the memory cell sub-arrays that are activated simultaneously and at which a power supply line along the row direction and a power supply line along the column direction have the same potential cross each other.
According to a ninth aspect of the invention, there is provided a semiconductor storage device comprising:
a memory cell array including a plurality of banks each having a plurality of memory cell sub-arrays in each of which a plurality of memory cells are arranged along row and column directions, and means for activating memory cells by designating addresses that are different for the respective banks;
a plurality of first power supplying lines extending along the row direction and arranged between the memory cell sub-arrays in the bank, for supplying a given potential; and
a plurality of second power supplying lines extending along the column direction, for supplying a given potential,
wherein at least one of the second power supplying lines is connected to the first power supplying line on a predetermined one of the banks, and supplies a potential to the predetermined bank.
According to a tenth aspect of the invention, there is provide a semiconductor storage device comprising:
a memory cell array in which a plurality of memory cells are arranged along row and column directions;
main word lines having at least two kinds of length, and extending in the row direction on the memory cell array; and
a spare main word line extending along the same direction as the main word lines, and having the same length as a longest one of the main word lines.
According to an eleventh aspect of the invention, there is provided a semiconductor storage device comprising:
a memory cell array in which a plurality of memory cells are arranged along row and column directions;
main word lines which extend along a row direction on the memory cell array, and one of which is selectively activated;
at least one sub-word line that branches off from the main word line;
at least one spare main word line extending along the same direction as the main word lines, and having the same length as a longest one of the main word lines; and
at least one spare sub-word line that branches off from the spare main word line.
According to a twelfth aspect of the invention, there is provided a semiconductor storage device comprising:
a memory cell array in which a plurality of memory cells are arranged along row and column directions;
main word lines which extend along a row direction on the memory cell array, and one of which is selectively activated;
at least one sub-word line that branches off from the main word line;
at least one spare main word line extending along the same direction as the main word lines;
at least one spare sub-word line that branches off from the spare main word line;
word line driver circuits formed at one predetermined ends of the respective main word lines, and arranged along the column direction in at least two columns; and
a spare word line driver circuit formed at one predetermined end of the spare main word line, and located at least in a column farthest from the memory cell array among the columns in which the word line driver circuits are arranged.
According to a thirteenth aspect of the invention, there is provided a semiconductor storage device comprising:
a memory cell array including a plurality of memory cell sub-arrays in each of which a plurality of memory cells are arranged in row and column directions;
main word lines which extend in the row direction on the memory cell sub-array, and one of which is selectively activated;
a dummy main word line which is activated at the same time as at least the main word line in the same memory cell sub-array is activated;
a dummy sub-word line that branches off from the dummy main word line;
a sense amplifier signal generating circuit formed at an end of the dummy sub-word line, for generating a sense amplifier activation signal at a time point when the end of the dummy sub-word line is activated, to thereby allow reading of information in the memory cell;
bit lines extending along the column direction, the memory cells being formed at positions where the bit lines cross the dummy sub-word line; and
sense amplifiers formed at ends of the bit lines.
According to a fourteenth aspect of the invention, there is provided a semiconductor storage device comprising:
a memory cell array in which a plurality of memory cells are arranged in row and column directions;
main word lines extending along the row direction on the memory cell array;
at least one spare main word line extending along the same direction as the main word lines;
a plurality of spare sub-word lines that extend in parallel with the main word lines and branch off from one of the spare main word lines; and
a dummy sub-word line that extends in parallel with at least one of the spare sub-word lines and to branches off from the spare main word line, for sensing a word line delay.
According to a fifteenth aspect of the invention, there is provided a semiconductor storage device comprising:
a memory cell array including a plurality of banks each having a plurality of memory cell sub-arrays in each of which a plurality of memory cells are arranged along row and column directions, and means for activating memory cells by designating addresses that are different for the respective banks;
main word lines extending in the row direction on the banks;
at least one spare main word line extending along the same direction as the main word lines;
a plurality of spare sub-word lines that branch off from the main word lines; and
a dummy sub-word line that extends in parallel with at least one of the spare sub-word lines and branches off from the spare main word line, for sensing a word line delay.